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SMPS-IC with MOSFET Driver Output
TDA 4916 GG
Features * * * * High clock frequency Low current drain High reference accuracy All monitoring functions
P-DSO-24-1
Type TDA 4916 GG
Ordering Code Q67000-A9230
Package P-DSO-24-1
Functional Description and Application The general-purpose single-ended switch-mode power supply device for the direct control of SIPMOS power transistors incorporates both digital and analog functions. These are required for the construction of high-quality flyback, forward and choke converters. The device can be likewise used for transformer-less voltage multipliers and variable-speed motors. Faults occurring during operation of the switch-mode power supply are detected by comparators integrated in the device which initiate protective functions. In addition, pairs of power supplies can be synchronized in antiphase. In-phase or antiphase synchronization is possible when more than two power supplies are involved.
Semiconductor Group
1
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TDA 4916 GG
Pin Configuration (top view)
P-DSO-24-1
Figure 1
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2
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Pin Definitions and Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol 0V GND Function GND Supply voltage Ground QSIP SIPMOS driver Supply voltage driver Series feed Current sensor negative input Current sensor K5 Current turn-OFF K6 Output K6 Pulse omission Soft start Input synchronization Output synchronization Frequency generator Frequency generator Ramp generator Input undervoltage Input overvoltage Input K1 Output operational amplifier Input operational amplifier Input operational amplifier Reference voltage
VS
0V QSIP Q SIP
VS QSIP
SF - I K5/- I K6 + I K5 + I K6 Q K6 PO
CSS
I SYN Q SYN
RT CT CR
I K4 I K3 I K1 Q OP - I OP + I OP
VREF
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3
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Figure 2 Block Diagram
Semiconductor Group 4 05.96
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Circuit Description The individual functional sections of the device and their interactions are described below. Power Supply at VS The device does not enable the output until the turn-ON threshold of VS is exceeded. The duty factor (active time/period) can then rise from zero to the value set with K1 in the time determined by the soft start. The turn-OFF threshold lies below the turn-ON threshold. Below the turn-OFF threshold the output Q SIP is reliably low. Frequency Generator The frequency is mainly determined by close-tolerance external components and the calibrated reference voltage. The switching frequency at the output can be set by suitable choice of Rt and Ct. The maximum possible duty factor can be reduced by a defined amount by means of a resistor from CT to 0V GND. The maximum possible duty factor can be increased by a defined amount by means of a resistor from CT to VS. Ramp Generator The ramp generator is controlled by the frequency generator and operates with the same frequency. Capacitor Cr on the ramp generator is discharged by an internally-set current and charged via a current set externally. The duration of the falling edge of the ramp generator output must be shorter than its rise time. Only then do the upper and lower switching levels of the ramp generator signal have their nominal values. In "voltage mode control" operation, the rising edge of the ramp generator signal is compared with an externally set dc voltage in comparator K1 for pulse-width control at the output. The slope of the rising edge is set by the current through Rr. The voltage source connected to Rr can be the SMPS input voltage. This makes it possible to control the duty factor for a constant volt-second product at the output. This control option (precontrol) permits equalization of known disturbances (e.g. input voltage ripple). Superimposed load current control (current mode control) can also be implemented. For this purpose the actual current at the source of the SIPMOS transistor is sensed and compared with the specified value in comparator K5.
Semiconductor Group
5
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TDA 4916 GG
Comparator K1 (duty factor setting for voltage mode control) The two plus inputs of the comparator are so connected that the lower plus level is always compared with the minus input level. As soon as the voltage of the rising edge of the sawtooth (minus input) exceeds the lower of the two plus input levels, the output is inhibited via the turn-OFF Flip-Flop, that is to say the High time of the output can be continuously varied. Since the frequency remains constant, this corresponds to a duty factor change. Comparator K2 The comparator has a switching threshold at 1.5 V. Its output sets the fault Flip-Flop when the voltage on capacitor Ca lies below 1.5 V. However, the fault Flip-Flop accepts the setting pulse only if no reset pulse (fault) is applied. This prevents resetting of the output as long as a fault signal is present. Comparators K3 (overvoltage), K4 (undervoltage), VS Undervoltage, VREF Overcurrent These are fault detectors which cause the output to be inhibited immediately by the fault Flip-Flop when faults occur. When faults are no longer present, the duty factor is reestablished via the soft start CSS. In the event of undervoltage, a current is injected at the input of K4 with the aid of which an adjustable hysteresis or latching is made possible. The value of the hysteresis is determined by the internal resistance of the external drive source and the current injected internally at the input of K4. In the event of undervoltage at K4, the injected current flows into the device. Comparator K5 (duty factor setting for current mode control) K5 is used to sense the source current at the switching transistor. The plus input of the comparator is fed out. Enabling of output Q SIP after cessation of the fault is effected with an H signal at the turn-OFF Flip-Flop output. Comparator K6 (overcurrent turn-OFF) The turn-OFF Flip-Flop is reset when overcurrent is detected by K6. In combination with the pulse-omission facility, individual pulses can then be omitted. This then results in a limited rise in the output current with a rising overload at the output.
Semiconductor Group
6
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Operational Amplifier OP Opamp OP is a high-quality operational amplifier. It can be used in the control circuit to transfer the variations in the voltage to be regulated in amplified form to the free plus input of comparator K1. As a result, a voltage change is converted into a duty factor change. The output of OP is an open collector. The frequency response of OP is already corrected. The plus input is connected internally via a capacitor to ground. This gives the inverting amplifier a more favorable phase response. Turn-OFF Flip-Flop AFF A pulse is fed to the set input of the turn-OFF Flip-Flop with the falling edge of the frequency generator signal. However, it can only really be set if no reset signal is applied. With a set turn-OFF Flip-Flop, the output is enabled and can be active. The Flip-Flop inhibits the output in the event of a turn-OFF signal from K1, K5, K6 or K7. Fault Flip-Flop Fault signals fed to the reset input of the fault Flip-Flop cause the output to be immediately disabled (Low), and to be turned on again via the soft start CSS after removing fault-condition. Soft Start CSS The smaller of the two voltages at the plus inputs of K1 - compared with the ramp generator voltage - is a measure of the duty factor at the output. At the instant the device is turned-ON, the voltage on capacitor CSS equals zero. Provided no fault exists, the capacitor is charged up to its maximum value.
CSS is discharged in the event of a fault. However, the fault Flip-Flop inhibits the output
immediately. Below a charging voltage of approx. 1.5 V, a set signal is applied to the fault Flip-Flop and the output is enabled, provided a reset signal is not applied simultaneously. However, since the minimum ramp generator voltage is about 1.8 V, the duty factor at the output is not actually slowly and continuously increased until the voltage on CSS exceeds a value of 1.8 V. The Z-diode limits the voltage on capacitor CSS. The voltage at the ramp generator can reach a higher level than the Zener voltage. With a suitable ramp generator rising edge slope, the duty factor can be limited to a wanted maximum value. Pulse Omission PO In the event of overcurrent in the SIPMOS transistors it is frequently necessary to omit pulses even with minimum duty factor. Only this measure ensures that the SIPMOS transistors cannot be overloaded. This wanted function can be achieved with Pulse Omission PO and Overcurrent Comparator K7 by means of a suitable external circuit.
Semiconductor Group
7
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Reference Voltage VREF The reference voltage source makes available a source with a high-stability temperature characteristic which can be used for external connection to the operational amplifier, the fault comparators, the frequency generator, or to other external units. The voltage source is short-circuit-proof to ground. Synchronization I SYN, Q SYN The device has an input and an output for synchronization. In the case of a synchronized device (slave), its output Q SIP is in phase opposition to the output Q SIP of the synchronizing device (master). In the case of an unconnected input I SYN, or with connection to VREF, or also when a series capacitor (without switching transitions) is connected, the device receives its clock from the internal frequency generator in accordance with the circuit connected to it. As soon as switching transitions appear at I SYN, switchover to external synchronization and vice versa takes place after a delay. After a switchover process, a few clock cycles must elapse in addition to the delay before the frequency and phase achieve their steady states. Series Feed SF The Series Feed circuit section is used to turn-OFF the external series-feed transistor when energy recovery commences. As a result there is minimum power loss in the supply to the device. With the series-feed transistor turned-OFF, its drive current flows via VS to VS. SIPMOS Driver Output Q SIP The output is High active. The time during which the output is active can be continuously varied. The duration of the rising edge of the frequency generator signal is the minimum time during which the output can be Low. The duration of the falling edge of the frequency generator signal is the maximum time during which the output can be High. The output driver is designed as a push-pull stage. The output current is limited internally to the specified values. Output Q SIP is connected via diodes to the supply VS QSIP and 0V QSIP. A protection circuit SS lies between Q SIP and GND to clamp the output to ground at low impedance in the event of undervoltage at VS.
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8
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When the supply to the switch-mode power supply is switched on, the capacitive displacement current from the gate of the SIPMOS transistor is conducted to the smoothing capacitor at VS QSIP by the diode connected to VS QSIP. The voltage at VS QSIP may reach about 2.3 V in the process without the SIPMOS transistor being turned-ON. The diode connected to ground clamps negative voltages at Q SIP to minus 0.7 V. Capacitive currents which occur with voltage dips at the drain terminal of the SIPMOS transistor can then flow away unimpeded. The output is active Low with supply voltages at VS and VS QSIP from about 4 V on. The function of the diode connected to VS QSIP and the resistor are then taken over by the pull-down source. The two ground terminals 0V SQIP and 0V GND can lie at different levels. This permits connections to be made to the SIPMOS transistor in such a way that the drive currents for the gate do not flow to the source via the current-sensing resistor. The maximum permissible level differences between 0V GND and 0V SQIP are given under Functional Range. If greater level differences are anticipated, it is better to join the two terminals.
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9
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Absolute Maximum Ratings
TA = - 40 to 85 C
Parameter Symbol Limit Values Unit Test Condition min. max. 17 17 5 3 5 5 3 V V V mA V V mA V mA V mA
VS,VVS QSIP - 0.3 Supply voltage; VS,VS QSIP - 0.3 I OP, I K1, I K3, I K4, I K5, I K6, VI 0 I SYN VI SYN -3 II SYN
Q SYN Frequency Generator; CT, RT Ramp Generator; CR Reference voltage; VREF
VI SYN > 5 V or VI SYN < 0 V
VQ SYN VCT, RT ICT, RT VCR ICR VREF IREF
- 0.3 - 0.3 0 - 0.3 0 - 0.3 - 10
VCRH
3 6 10
VCT > 5 V VCRH (see charact.) VCR > VCRH VREF > 6 V or VREF < - 0.3 V
Output Opamp; Q OP Inhibited Conducting Output Overcurrent Turn-OFF; Q K6 Inhibited Conducting Driver output; Q SIP Q SIP clamping diodes Soft start; CSS Pulse omission; PO Series feed; SF Junction temperature Storage temperature Thermal resistance system - ambient
VQ OP IQ OP
- 0.3 0
17 5
V mA
VQ K6 IQ K6 VQ SIP IQ SIP VCSS ICSS VPO IPO VSF Tj Ts Rth S/A
- 0.3 0 - 0.3 - 10 - 0.3 0 - 0.3 0 - 0.3 - 65 - 65
17 5
V mA V mA V A V mA V C C K/W
1)
VS
10
VSSH
100
VPOH
3 17 150 150 60
VQ SIP > VS or VQ SIP < - 0.3 V VSSH (see charact.) VSS > VSSH VPOH (see charact.) VPO > VPOH
The values refer to the two connected ground terminals. 1) Important: observe max. power loss or junction temperature.
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10
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Operating Range Function Supply voltage Frequency generator Ramp generator Ambient temperature Ground Q SIP Resistor at RT Symbol min. Limit Values max. 15 15 400 400 + 100 1000 V V kHz kHz C V k 0 0 0.05 0.05 - 40 27 Unit
VS VVS QSIP f f TA V0V QSIP RRT
GND - 300 mV GND + 2 V
Characteristics
VSon < VS < 15 V, - 25 C < TA < 85 C; VSon means that VS has exceeded VSH, but has not gone below VSL.
Parameter Current in VS Symbol min. Limit Values typ. max. 7 8 mA1) mA1) FG at 100 kHz FG at 300 kHz Q SYN unconnected FG at 100 kHz FG at 300 kHz Q SYN to 0V GND FG at 100 kHz FG at 300 kHz FG at 100 kHz FG at 300 kHz Q SYN unconnected FG at 100 kHz FG at 300 kHz Q SYN to 0 V GND Unit Test Condition
IVS
8 9 Current in VS QSIP Current in VS + VS QSIP
mA1) mA1) mA1) mA1)
IVS QSIP ISum
2.5 5.5 9 13
mA1) mA1)
10 14
mA1) mA1)
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11
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Characteristics (cont'd)
VSon < VS < 15 V, - 25 C < TA < 85 C; VSon means that VS has exceeded VSH, but has not gone below VSL.
Parameter Symbol min. Current Drain2) Hysteresis at VS Turn-ON threshold for VS rising Turn-OFF threshold for VS falling
1) 2)
Limit Values typ. max.
Unit
Test Condition
VSH VSL
8.0 7.9
9.1 9.0
10 9.9
V V
CT; RT (see oscillator nomogram). The currents as VS and VS QSIP are in each case without loads and without internal discharge to CR, as well as with active output Q SIP.
Reference Voltage Voltage Load current Voltage change Voltage change Temperature response Operate threshold VREF overcurrent
VREF
- IREF VREF VREF VREF/ T - IREFO
2.460 0
2.500 2.540 3 5 3 0.1
V mA mV mV mV/K
IREF = 250 A; VS = 12 V
VREF < 30 mV
0 mA < IREF < 500 A 12 V < VS < 14 V
3
6
10
mA
Frequency Generator Nominal frequency spread fF/fO -4 4 % 20 kHz < fO < 150 kHz; Q SYN to GND; VS = 12 V; TA = 25 C 10 V < VS < 14.4 V; TA = 25 C; relative to
Voltage dependence fV/fO of nominal frequency
-1
1
%
fO at 12 V; 20 kHz < fO
< 150 kHz
Semiconductor Group
12
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TDA 4916 GG
Characteristics (cont'd)
VSon < VS < 15 V, - 25 C < TA < 85 C; VSon means that VS has exceeded VSH, but has not gone below VSL.
Parameter Temperaturedependence of nominal frequency Symbol min. f/fO -3 Limit Values typ. max. 3 % - 25 C < TA < + 85 C; VS = 12 V; relative to fO at 25 C; 20 kHz < fO < 150 kHz 20 kHz to 150 kHz Unit Test Condition
Nominal frequency Nominal frequency Nominal frequency
f20150 f150250 f250300
0.92 fO 0.88 fO 0.85 fO 48 46 44
fO fO fO
1.08 fO kHz1)
1.12 fO kHz1),2) 150 kHz to 250 kHz 1.15 fO kHz1),2) 250 kHz to 300 kHz 52 54 56 %2) %2) %2) 20 kHz to 150 kHz 150 kHz to 250 kHz 250 kHz to 300 kHz
Maximum duty cycle 20150 Maximum duty cycle 150200 Maximum duty cycle 250300 Ramp Generator
f Maximum voltage at VCRH CR Minimum voltage VCRL at CR Discharge current at Idis CR Capacitance at CR CR
ON-time spread (limited by CSS) tOt/tOt
Frequency range
0.05 4.8 1.4 0.75 10 -9 5.8 1.8 1.00
300 6.8 2.2 1.25
kHz V V mA pF internally fixed
9
%
Cr = 200 pF; VIK1 > VSSH; IRr = 150 A; TA = 25 C;
relative to tOt = 4.0 s
1) 2)
CT; RT (see oscillator nomogram). See diagram: Tolerance of oscillator frequency, duty cycle.
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13
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TDA 4916 GG
Characteristics (cont'd)
VSon < VS < 15 V, - 25 C < TA < 85 C; VSon means that VS has exceeded VSH, but has not gone below VSL.
Parameter ON-time drift Symbol min. tOt/tOt -2 Limit Values typ. max. 2 % Unit Test Condition
Cr = 200 pF; VIK1 > VCAH; IRr = 150 A;
relative to tOt = 25 C
ON-time spread
tOt
3.6
4.0
4.4
s
Cr = 200 pF; VIK1 > VCAH; IRr = 150 A
Operational Amplifier OP Open-loop gain
Go Input offset voltage Vio Input current - Ii Input common-mode Vcm
range
60 -5 - 0.2 -3 0.5 2 90 - 10 1
80
100 +5 1 4
dB mV A V mA
IQ OP = 100 A IQ OP = 100 A
Output current Output voltage Transit frequency Transit phase Temp. coeff. of Vio Rate of rise of voltage at output Comparator K1 Input current
IQ OP VQ OP ft
t
0.5 < VQ OP < 15 V 0 mA < IQ OP < 2 mA
15 5 120 3 8 150 + 10 6
V MHz Deg. V/K V/s
Tc
V/t
IQ OP = 100 A
- IK1 0 200
1
A V ns1) Nominal load 1 nF at Q SIP
Input common-mode Vcm range Turn-OFF delay
1)
VCAH
400
tOFF
Step function V - 100 mV
V + 100 mV (for delay from comparator input to Q SIP).
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14
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Characteristics (cont'd)
VSon < VS < 15 V, - 25 C < TA < 85 C; VSon means that VS has exceeded VSH, but has not gone below VSL.
Parameter Symbol min. Overvoltage K3 Input current Switching voltage Turn-OFF delay Undervoltage K4 Input current at K4 Switching voltage at K4 Hysteresis current Turn-OFF delay - Ii 0.2 A - Ii 0.2 A Limit Values typ. max. Unit Test Condition
VSW tOFF
VREF - 5 mV
1 2
VREF + V 5 mV
4 s
VSW Ihy4H Ihy4L to
VREF - 5 mV
5 1 10 2
VREF + V 5 mV
15 0.1 4 A A s1)
V+ IK4 < Vsw V+ IK4 > Vsw
Current Sensor K5; Overcurrent Turn-OFF K6 Input current Input offset voltage Input common-mode range Turn-OFF delay Output K6 inhibited Conducting
1) 2) 3)
- Idyn
1 -5 0 +5 4
A mV V
Vio Vcm
tOFF IQK6 VQK6
150 250
300 400 2 1.2
ns2) ns3) A V
Load 1 nF at Q SIP
VQK6 = 5 V IQK6 = 1 mA
Step function VREF - 100 mV Step function V - 100 mV Step function V - 10 mV
VREF + 100 mV (for delay from comparator input to Q SIP). V + 100 mV (for delay from comparator input to Q SIP). V + 10 mV (for delay from comparator input to Q SIP).
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15
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Characteristics (cont'd)
VSon < VS < 15 V, - 25 C < TA < 85 C; VSon means that VS has exceeded VSH, but has not gone below VSL.
Parameter Symbol min. Soft Start CSS Charging current at CSS - Ich 4 0.8 4.4 0.1 1.1 1.4 1.7 5 1.5 4.8 8 3.0 5.2 A A V V V Limit Values typ. max. Unit Test Condition
Discharge current at Idis
CSS
Upper clamping voltage Difference VCRH - VSSH
VSSH VDSS
VCRH - VSSH
Switching voltage of VK2 K2 Pulse Omission PO Charging current at PO int. Charging current at PO ext. Voltage at - K7 Upper clamping voltage at + K7 Minimum voltage applied to PO Synchronization Input I SYN Switching threshold at I SYN Open Rising edge Falling edge - Ich
4
6
9 1
A mA V V V 0 mA < IPO < 1 mA
Ich V- K7 VPOH VPOM VS/3
-5%
VS/3 V-K7
+ 0.7
VS/3
+5%
V-K7
+ 0.2 1
V-K7
+ 1.2
II SYN
- 70
200
A
0 V< VI SYN < 4.5 V
VI SYNO VI SYNR VI SYNF
1.5 2.5 1.0
2.7 3.4 2.0
3.5 4.0 3.0
V V V
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16
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Characteristics (cont'd)
VSon < VS < 15 V, - 25 C < TA < 85 C; VSon means that VS has exceeded VSH, but has not gone below VSL.
Parameter Symbol min. Switchover delay int. tdf-s free-running synchronized synchronized tds-f free-running Limiting diodes Output Q SYN High Low Fan-out of Q SYN for control I SYN Series Feed Series Feed Threshold at VS - II SYN II SYN 15 9 0 0 4.1 0.6 2 Limit Values typ. 35 18 max. 60 35 2 2 s s mA mA V V Unit Test Condition
VI SYN < 1 V VI SYN > 5 V
- 500 A < IQ SYN < 0 A 0 A< IQ SYN < 500 A Q SYN to 0V GND allowed
VQ SYNH VQ SYNL
VSFTH VSFGAP ISF max VZ11 VZ12
9.0 500 500 5 -
10.0 - - - -
10.5 - - - 8
V mV A V V
ISF > 5 A; VSF = 13 V VS = 11.5 V; VSF = 12.5 V IZ1 = 20 A; 0 VS 8 V IZ1 = 500 A 0 VS 8 V
VSH to VSFTH Gap
Maximum current Voltage at Z1 Voltage at Z1
Output Driver Q SIP Saturation voltage source
VQ SIPH VQ SIPH VQ SIPH VQ SIPL VQ SIPL
1.8 2.2 2.5 0.1 1.7
2.0 2.5 3.0 0.5 2.2
V V V V V
Saturation voltage sink
IQ SIP = 0 mA IQ SIP = - 1 mA IQ SIP = - 200 mA VS = VQ SIP > VSon IQ SIP = 10 mA IQ SIP = 200 mA VS = VQ SIP > VSon
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17
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Characteristics (cont'd)
VSon < VS < 15 V, - 25 C < TA < 85 C; VSon means that VS has exceeded VSH, but has not gone below VSL.
Parameter Saturation voltage sink Output current Falling edge Rising edge Output voltage Fall time Rise time
1) 2)
Symbol min.
Limit Values typ. max. 1.5
Unit V
Test Condition
VQ SIPP
IQ SIP = + 5 mA IC passive CQ SIP = 10 nF; VS = VQ SIP = 12 V CQ SIP = 10 nF; VS = VQ SIP = 12 V CQ SIP = 10 nF; VS = VQ SIP = 12 V CQ SIP = 10 nF; VS = VQ SIP = 12 V
IQ SIP
- IQ SIP
0.7 0.7
1.0 1.0
1.5 1.5
A1) A1)
tQ SIPF tQ SIPR
200 200
ns2) ns2)
Maximum dynamic current during rising or falling edge. Voltage level 10 %/90 %.
Semiconductor Group
18
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Figure 3 Application Circuit 1: Forward Converter with Output Regulation
Semiconductor Group 19 05.96
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Figure 4 Application Circuit 2: Flyback Converter with EMF Regulation
Semiconductor Group 20 05.96
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Figure 5 Timing Diagram
Semiconductor Group 21 05.96
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Figure 6 Soft Start CSS / Fault/ON - OFF
Semiconductor Group 22 05.96
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Nomogram for FG
fo = 97.5 kHz @ Tj = 25 C; RT = 40.2 k; CT = 560 pF
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23
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Instructions for the Approximate Calculation of the Maximum Duty Cycle of the FG when RVS or RGND is Connected to Input CT. 1. General remarks Duty cycle = ON time/period Time t = CT VCT/ICT VCT = approx. 0.6 V Current IRGND = 2.2 V/RGND Current IRT = 2.5 V/RT Current IRVS = (12 V - 2.2 V)/RVS Mean value VCT Mean = approx. 2.2 V To facilitate better general understanding, the equations are not abbreviated in the following. The wanted quantity can be isolated using the rules of arithmetic. 2. Calculation for connection of RVS ( > 0.5)
----------------------------I RT - I RVS max = ----------------------------------------------------------------------------------------------- + -----------------------------I RT - I RVS I RT + I RVS
CT 0.6 V
CT 0.6 V
C T 0.6 V
3. Calculation for connection of RGND ( < 0.5)
-----------------------------------
max = ------------------------------------------------------------------------------CT 0.6 V C T 0.6 V
CT 0.6 V I RT + I RGND
----------------------------------- + -----------------------------------
I RT + I RGND I RT - I RGND
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24
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Duty Cycle Limiting fFG = 100 kHz Example for max = 44 %: Step to get 44 % a resistor RGND = 220 k is found Step for the same we get RT = 39 k to set fFG to 100 kHz
Semiconductor Group
25
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Tolerance of Osc. Frequency fmax versus Osc. Frequency f
Tolerance of Duty Cycle max versus Osc. Frequency f
Semiconductor Group
26
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Package Outlines P-DSO-24-1 (SMD) (Plastic Dual Small Outline Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 27
Dimensions in mm 05.96
GPS05144

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